There is known a semiconductor substrate having a SiGe gradient composition layer formed on a Si substrate with Ge concentration therein increasing with the thickness, a SiGe constant composition layer with constant Ge concentration formed thereon, and another Si layer (strained Si layer) formed thereon (Hereinafter, the SiGe gradient composition layer and SiGe constant composition layer will be, if collectively referred to, termed “SiGe layer”. A semiconductor substrate having such a structure may be hereinafter sometimes referred to as “strained Si substrate”). Since the SiGe layer has a larger lattice constant than the Si layer and expands the lattice constant of the Si layer thereby generating tensile strain, which in turn improves electron and hole mobility, application of such a substrate in electronic devices such as MOSFET (metal oxide semiconductor field effect transistor) is known to be effective in increasing their performance. However, conventional strained Si substrates had problems such as generation of dislocations due to the difference in lattice constant between the Si substrate and the SiGe layer, and generation of irregularities such as cross hatch patterns on the surface. A MOSFET fabricated using a strained Si substrate with such a strained Si layer of poor quality would exhibit performance that was not as improved as expected.
As a measure to solve such a problem, a published Japanese translation of PCT International Application No. 2000-513507 proposes a method in which irregularities on the surface of a SiGe layer are flattened by CMP (chemical mechanical polishing) or the like and a strained Si layer is grown on the flattened surface of the SiGe layer.
However, when epitaxially growing a strained Si layer on the surface of a SiGe layer that has been flattened by CMP or the like as in this case, there was a problem that surface flatness of the strained Si layer may be degraded.